The present invention generally relates to debugging hardware and software arrangements, and more particularly to debugging run-time reconfigurable processing arrangements.
Logic cores are generally used as building blocks in creating electronic circuit designs. A logic core typically is a design that when implemented in hardware performs a predetermined function and which has input and output signal lines that can be connected to other logic. For example, one particular logic core may implement a digital filter, and another logic core may implement a constant multiplier.
The traditional tools for creating logic cores generally support design entry via schematics or a hardware description language such as HDL or VHDL. In addition, there are a multitude of proprietary languages for creating logic cores that are specifically suitable for a particular family of devices. Some environments, for example VHDL, support creation of test environments along with the design itself.
In the context of programmable logic devices (PLDs), for example, field programmable gate arrays (FPGAs) from Xilinx, there are numerous tools available for testing the functionality of circuits created from logic cores. The tools include functional and physical simulators, BoardScope(trademark) graphical debugger software, and XHWIF(trademark) hardware interface software.
New developments in the area of creating designs for PLDs are rendering the prior test methodologies and tools inadequate. For example, circuit designs, including run-time parameterizable logic core generators, can be created in the JBits(trademark) environment from Xilinx. The JBits environment is a Java-based tool that includes an application programming interface (API) that allows designers to develop logic and write a configuration bitstream directly to a Xilinx FPGA. The JBits API permits the FPGA bitstream to be modified quickly, allowing for fast reconfiguration of the FPGA. In a run-time reconfiguration system, circuits are configured and then reconfigured based on information supplied in real-time by user software, user data, or sensor data. With Virtex FPGAs, the JBits API can be used to partially or fully reconfigure the internal logic of the hardware device. The JBits environment also supports run-time reconfiguration of FPGAs and also configuration of FPGAs over a communications network, for example, an intranet or the Internet.
Run-time reconfigurable systems are generally co-processor systems. A host processor executes a run-time reconfiguration program, and the run-time reconfiguration program implements application functions on the host processor, defines a circuit design, creates configuration data, and configures the FPGA. Since the host processor- and the FPGA are likely to be independently clocked, debugging a co-processor system is difficult.
Current techniques for debugging co-processor systems generally involve using simulators on the FPGA circuit and/or debug cores inserted into HDL logic. Simulation does not support real-time debugging. While debug cores support real-time debugging, debug cores are static and provide little user control over the structure. Neither simulation nor debug cores provides a suitable environment for debugging co-processor arrangements.
A system and method that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
In various embodiments, a system and method are provided for debugging a run-time reconfigurable processing arrangement. The processing arrangement includes a host process that hosts a run-time reconfiguration application program and a programmable logic device (PLD). The run-time reconfiguration program specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data. One of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles. When the PLD is activated, the breakpoint circuit steps the PLD, and state information of one or more selected elements of the PLD is analyzed after stepping the PLD. Depending on the analysis, the breakpoint core generator is re-parameterized and the PLD reconfigured with a new breakpoint circuit to continue debugging.
It will be appreciated that various other embodiments are set forth in the Detailed Description and claims which follow.